Method and apparatus for decoding BCH code

ABSTRACT

Apparatus for decoding BCH code can correct double errors using a modification of the Chien search method. This decoding apparatus comprises circuits to form syndromes S1 and S3; a circuit to form S12; a circuit to form S13; a circuit to form (S13+S3); and Chien search circuit, in which the error-location polynomial  sigma (x)=(S1x2+S12x+S13+S3) is solved, thereby correcting errors of two or less. With this apparatus, there is no need to perform a dividing process, and a high decoding processing speed can be realized without using any PLA or ROM.

BACKGROUND OF THE INVENTION Field of the Invention and Related ArtStatement

The present invention relates to an apparatus for decoding BCH(Bose-Chaudhuri-Hocquenghem) code capable of correcting double errors,by use of a Chien search method.

As one of the methods of decoding the BCH code which can correct doubleerrors, there has been known a decoding method whereby two syndromes S1and S3 are formed from the receiving sequence and then theerror-location polynomial

    σ(x)=x.sup.2 +S1 x+S1.sup.2 +(S3/S1)

is solved by the method called the Chien search method, therebycorrecting the errors in the receiving sequence.

In this decoding process, the calculation of the syndromes S1 and S3 andthe calculation of S1² can be relatively easily realized due to ahard-wired logic arrangement such as a gate array or the like. However,the dividing process of S3/S1 needs complicated calculations. Therefore,the method is performed using a dividing process performed using a ROMwhich limits the speed of operation which can be obtained.

When the decoding apparatus is in the form of an LSI, with the dividingcircuit constituted by a PLA, the scale of the LSI chip is enlarged,which is a drawback. On the other hand, when dividing circuit isconstituted by a ROM, the decoding processing time is restricted due tothe access time, resulting in the drawback that the decoding processcannot be executed at a high speed.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide anapparatus for decoding BCH code which is suitable for LSI realization,without using any ROM or PLA.

According to the invention, there is provided a decoding apparatus ofBCH code capable of correcting double errors by use of the Chien searchmethod comprising:

circuits to form syndromes S1 and S3;

a circuit to form S1² ;

a circuit to form S1³ ;

a circuit to form (S1³ and S3); and

a Chien search circuit,

wherein the error-location polynomial σ'(x) (=S1 x² +S1² x+S1³ +S3) issolved, thereby correcting errors of two or less.

By using the polynomial (σ'(x)=S1 x² +S1² x+S1³ +S3) as theerror-location polynomial, the term for the dividing process of (S3/S1)is removed from the error-location polynomial, and the error-locationpolynomial is solved, thereby obtaining the error locations andcorrecting the errors, without dividing. Therefore, there is no need toperform the dividing process of (S3/S1), and the decoding apparatushaving a simple constitution and a high decoding processing speed can berealized without using any PLA or ROM.

The above and other objects, features and advantages of the presentinvention will be more clear from the following description withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of an illustrative embodiment ofthe present invention;

FIG. 2 is a block diagram of a circuit to form the syndrome S1;

FIG. 3 is a block diagram of a circuit to form the syndrome S3;

FIG. 4 is a block diagram of a circuit to form S1² ;

FIG. 5 is a block diagram of a circuit to form S1³ ;

FIG. 6 is a block diagram of a circuit to form (S1³ +S3);

FIG. 7 is a block diagram of a circuit to multiply α⁻² ; and

FIG. 8 is a block diagram of a circuit to multiply α⁻¹.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In FIG. 1, a receiving sequence is applied to an input terminal 1. Thereceiving sequence is supplied to an S1 forming circuit 2 and an S3forming circuit 3 and the syndromes S1 and S3 are formed. The syndromesS1 and S3 are supplied to a zero detecting circuit 4. The zero detectingcircuit 4 generates a detection signal of a low level "L" when all ofthe digits of the syndromes S1 and S3 are "0", namely, when no error isdetected. This detection signal is supplied into a latch circuit 4Asynchronously with the receiving sequence.

The syndrome S1 is supplied to an S1² forming circuit 5 and an S1³forming circuit 6 and the values of S1² and S1³ are produced. The S1³forming circuit 6 multiplies S1² with S1 to produce S1³ as will beexplained hereinafter. The syndromes S3 and S1³ are supplied to anarithmetic operating circuit 7, by which (S1³ +S3) is formed.

In this manner, the respective coefficients S1, S1², S1³, and S3 of theerror-location polynomial σ'(x) are obtained and supplied to a Chiensearch circuit 8 for performing the process of the Chien search. TheChien search circuit 8 is shown as the region surrounded by the brokenline in FIG. 1 and comprises: arithmetic operating circuits 9 and 12;delay circuits 10 and 13, each having the delay time of one clock pulse;switching circuits 11 and 14; an adding circuit 15; and a zero detectingcircuit 16. The switching circuits 11 and 14 respectively select thesyndrome S1 from the S1 forming circuit 2 and S1² from the S1² formingcircuit 5 at the time of the head bit of the receiving sequence. Theswitching circuits 11 and 14 respectively select outputs of the delaycircuits 10 and 13 with respect to the remaining bits. Control of theswitching circuits 11 and 14 is accomplished by a conventional circuitfor generating timing control signals, operating in synchronism with thereceiving sequence.

Outputs of the switching circuits 11 and 14 are supplied to thearithmetic operating circuits 9 and 12, respectively. Outputs of theoperating circuits 9 and 12 are supplied to the delay circuits 10 and13, respectively. In this way, the cyclic consititution is obtained. Theoperating circuit 9 multiplies α⁻² and the operating circuit 12multiplies α⁻¹. α is the root of the generator polynomial over GF(2^(m)). Assuming that a code length is n, the term of S1 α^(-2n) isobtained by the operating circuit 9 and the term of S1² α^(-n) isderived by the operating circuit 12. The outputs of the operatingcircuits 9 and 12 are supplied to the adding circuit 15 to perform theaddition of (mod 2).

The adding circuit 15 executes the arithmetic operation of theerror-location polynomial (σ'(x)=S1 x² +S1² x+S1³ +S3). An output of theadding circuit 15 is supplied to the zero detecting circuit 16. Theposition where the output of the adding circuit 15 becomes zero is theerror location. The zero detecting circuit 16 generates a correctioninstructing signal which becomes a high level "H" at the error location.

The correction instructing signal from the zero detecting circuit 16 issupplied to an AND gate 17 together with an output of the latch circuit4A. The output of the latch circuit 4A becomes a low level "L", due tothe zero detecting circuit 4, when all digits of both of the syndromesS1 and S3 are "O". When (S1=S3=O), the result of the operation of theerror-location polynomial becomes zero, so that the correctioninstructing signal which signals an error is generated from the zerodetecting circuit 16. The AND gate 17 is provided to inhibit an impropercorrection instruction signal.

The correction instructing signal of "H" from the AND gate 17 issupplied to an exclusive OR gate (hereinafter referred to as EX-OR gate)18. The bits of the receiving sequence from a shift register 19 areinverted by the EX-OR gate 18 in response to the correction instructingsignal which is generated in correspondence to the error location, sothat the bit errors are corrected. The error-corrected data sequencefrom the EX-OR gate 18 is taken out to an output terminal 20. The shiftregister 19 delays the receiving sequence by the period of timenecessary for detection of the error location.

The invention can be applied to decode, for example, the (15, 7) BCHcode, which (15) denotes the code length and (7) is the information bitlength and the minimum distance is 5. Therefore, the errors of two bitsor less can be corrected. The generator polynomial of this code is##EQU1## Assuming that α is the root of (x⁴ +x+1)=0, the minimalpolynomial having α³ as the root is (x⁴ +x³ +x² +x+1). The elements overthe Galois Field GF(2⁴) which is given by (x⁴ +x+1)=0 are as follows.

    ______________________________________                                                  α.sup.3                                                                     α.sup.2                                                                             α.sup.1                                                                       α.sup.0                                 ______________________________________                                           0        0     0           0   0                                           α.sup.0                                                                             0     0           0   1                                           α.sup.1                                                                             0     0           1   0                                           α.sup.2                                                                             0     1           0   0                                           α.sup.3                                                                             1     0           0   0                                           α.sup.4                                                                             0     0           1   1                                           α.sup.5                                                                             0     1           1   0                                           α.sup.6                                                                             1     1           0   0                                           α.sup.7                                                                             1     0           1   1                                           α.sup.8                                                                             0     1           0   1                                           α.sup.9                                                                             1     0           1   0                                            α.sup.10                                                                           0     1           1   1                                            α.sup.11                                                                           1     1           1   0                                            α.sup.12                                                                           1     1           1   1                                            α.sup.13                                                                           1     1           0   1                                            α.sup.14                                                                           1     0           0   1                                           ______________________________________                                    

The parity-check matrix H of this code is shown below. ##EQU2##

FIG. 2 shows an example of the S1 forming circuit 2 to form the syndromeS1. The syndrome can be obtained by calculating γ(α^(j)) with respect tothe receiving code word

    γ(x)=γ0+γ.sup.1x+. . . . . .+γ14x.sup.14

The S1 forming circuit 2 calculates (j=1), namely, γ(α). As shown inFIG. 2, with respect to the receiving sequence from an input terminal21, flip-flops 22, 23, 24 and 25 each having the delay time of one clockare cascade-connected. In the case of the polynominal (x⁴ +x+1), anadding circuit 26 is inserted between the input terminal 21 and theflip-flop 22. The adding circuit 26 performs the addition of (mod 2) andmay be realized by an EX-OR gate. All of the following adding circuitsare similarly the adding circuits of (mod 2).

The additions of (mod 2) are as follows:

    0⊕0=0

    0⊕1=1

    1⊕0=1

    1⊕1=0

An adding circuit 27 is also provided between the flip-flops 22 and 23.An output of the flip-flop 25 is fed back to the adding circuits 26 and27, respectively.

When a "1" signal is provided to the input terminal 21 and the shiftregisters consisting of the flip-flops 22 to 25 are sequentiallyshifted, the binary expressions of α⁰, α¹, ---, α¹⁴ are provided outputsfrom the flip-flops, respectively. Therefore, by sequentially providing,as inputs, the receiving sequence γ14, γ13, ---, γ0 to the inputterminal 21, the syndrome S1 (a0, a1, a2, a3) is obtained.

FIG. 3 shows an example of the S3 forming circuit 3 to form the syndromeS3. The S3 forming circuit 3 calculates (j=3), namely, γ(α³). Fourflip-flops 32, 33, 34, and 35 are provided. Adding circuits 36, 37, 38,and 39 are also provided on the input sides of the flip flops 32 to 25,respectively. The receiving sequence from an input terminal 31 and anoutput of the flip-flop 33 are supplied to the adding circuit 36.Outputs of the flip-flops 33 and 34 are supplied to the adding circuit37. Outputs of the flip-flops 34 and 35 are supplied to the addingcircuit 38. Outputs of the flip-flops 35 and 32 are supplied to theadding circuit 39.

By sequentially providing the receiving sequence γ14, γ13, ---, γ⁰ tothe input terminal 31, the syndrome S3 (d0, d1, d2, d3) is obtained.

FIG. 4 shows an example of the S1² forming circuit 5 to form the squareof the syndrome S1 (a0, a1, a2, a3). The S1² forming circuit 5 comprisesan adding circuit 41 which is supplied with a0 and a2 and an addingcircuit 42 which is supplied with a1 and a3. Assuming that S1² is (b0,b1, b2, b3) then b0 is the output from the adding circuit 41, and a2 isconnected to the output as b1; b2 is connected to the output from theadding circuit 42 and a3 is connected to the output as b3.

FIG. 5 shows an arrangement of an example of the S1³ forming circuit 6.The syndrome S1 (a0, a1, a2, a3) produced by the S1 forming circuit 2 isprovided to an input terminal 51. Adding circuits 56, 57, 58, and 59 areprovided on the input sides of four flip-flops 52, 53, 54, and 55 whichare cascade-connected, respectively. An output of the flip-flop 55 isfed back as one input of each of the adding circuits 56 to 59. Outputsof multiplying circuits 61, 62, 63, and 64, to execute themultiplications of (mod 2), are supplied as the other inputs of theadding circuits 56 and 57, respectively.

The multiplications of (mod 2) are as follows:

    0·0=0

    0·1=0

    1·0=0

    1·1=1

The syndrome S1 from the input terminal 51 is supplied to one input ofeach of the multiplying circuits 61 to 64, and s1² (b0, b1, b2, b3) issupplied to the other inputs of the multiplying circuits 61 to 64,respectively. S1³ (c0, c1, c2, c3) is generated as outputs of theflip-flops 52 to 55, respectively. Namely, the S1³ forming circuit of 6FIG. 5 multiplies S1² with S1.

An explanation is made hereinbelow as to the product C of two elements Aand B over the Galois Field, which can be derived by the S1³ formingcircuit 6 of FIG. 5.

First, it is assumed that the elements A and B are expressed by thefollowing polynomial expressions.

    A=a3 α.sup.3 +a2 α.sup.2 +a1α+a0

    B=b3 α.sup.3 +b2 α.sup.2 +b1α+b0

The product C of the elements A and B is as shown below. ##EQU3##

The flip flops 52 to 55 are sequentially shifted for every clock fromthe initial state. The output C"' becomes

    C"'=c3

by the first shift. The output C" becomes

    C"=c3α+c2

by the second shift. The output C' becomes ##EQU4## by the third shift.The output C becomes ##EQU5## by the fourth shift. In this manner, themultiplications are completed.

The case where (A=α³) and (B=α⁶) will be described as practical example.These values are represented by the following binary expressions.

    (a3, a2, a1, a0)=(1 0 0 0)

    (b3, b2, b1, b0)=(1 1 0 0)

When the shifting operations are sequentially performed from the initialstate, the outputs (c3, c2, c1, c0) change as shown in the followingtable.

    ______________________________________                                                Input     c3    c2       c1  c0                                       ______________________________________                                        Initial state                                                                           1           0     0      0   0                                      First shift                                                                             1           1     0      0   0                                      Second shift                                                                            0           1     0      1   1                                      Third shift                                                                             0           0     1      0   1                                      Fourth shift                                                                            --          1     0      1   0                                      ______________________________________                                    

As will be obviously understood from this table, the multiplicationoutput of (α³ xα⁶ =α⁹ =1 0 1 0) can be obtained by performing theshifting operations four times.

Different from the case where S1³ is directly obtained from the syndromeS1, the S1³ forming circuit 6 in this embodiment derives S1³ bymultiplying both S1 and S1². Consequently, the circuit constitution canbe remarkably simplified.

As shown in FIG. 6, in the arithmetic operating circuit 7 which obtains(S1³ +S3), the corresponding bits of S3 (=c0, c1, c2, c3) and S1³ (=d0,d1, d2, d3) are respectively supplied to adding circuits 71, 72, 73, and74. The binary expressions (e0, e1, e2, e3) of (S1³ +S3) are derivedfrom the adding circuits 71 to 74.

The arithmetic operating circuit 9 to multiply the syndrome S1 (a3, a2,a1, a0) with α⁻² comprises adding circuits 81 and 82 as shown in FIG. 7;a0 and a1 are supplied to the adding circuit 81. An output of the addingcircuit 81 and a2 are supplied to the adding circuit 82. The output ofthe adding circuit 82 is A0, the input a3 is A1, the input a0 is A2, andthe output of the adding circuit 81 is A3. Namely, ##EQU6##

The arithmetic operating circuit 12 to multiply S1² (b3, b2, b1, b0)with α⁻¹ comprises an adding circuit 83 as shown in FIG. 8. b0 and b1are supplied to the adding circuit 83. An output of the adding circuit83 is B0, the input b2 is B1, the input b3 is B2, and the input b0 isB3. Namely, ##EQU7##

According to the present invention, since there is no need to calculatethe term of division of (S3/S1) in the error-location polynomial σ (x),it is unnecessary to use any dividing circuit embodied in complicatedhard-logic, or any dividing circuit using a ROM, which restricts thedecoding processing speed of the whole decoding apparatus. Consequently,it is possible to realize the decoding apparatus having a simpleconstitution and a hard-wired logic arrangement such as a gate array orthe like, which is suitable for production in the form of an LSI.

Although the present invention has been shown and described with respectto preferred embodiments, various changes and modifications which areobvious to a person skilled in the art to which the invention pertainsare deemed to lie within the spirit and scope of the invention.

What is claimed is:
 1. An apparatus for decoding BCH codecomprising:first and second circuits to form syndromes S1 and S3,respectively, from a receiving sequence; a third circuit connected withsaid first circuit to form S1² from the syndrome S1; a fourth circuitconnected with said first and third circuits to form S1³ from thesyndrome S1; a fifth circuit connected to form (S1³ +S3); and a Chiensearch circuit connected with said first, third and fifth circuits toreceive said S1, S1², and (S1³ +S3), and to solve the error-locationpolynomial

    (σ(x)=S1 x.sup.2 +S1.sup.2 x+S1.sup.3 +S3)

thereby correcting errors of two or less in said receiving sequence. 2.An apparatus for decording BCH code according to claim 1, wherein saidfourth circuit to form S1³ multiplies S1² with S1.
 3. An apparatus fordecoding BCH code according to claim 1, including a zero detectingcircuit which is supplied with said syndromes S1 and S3, and a gatingcircuit connected to said zero detecting circuit to inhibit an output ofsaid Chien search circuit when both of said syndromes S1 and S3 are 0.4. A method for decoding BCH code, including the steps of first formingthe syndrome S1 and S3 from a receiving sequence, then forming S1² andS1³ from S1 and S1² respectively, combining said syndromes to form (S1³+S3), and using a Chien search circuit to produce an output signalcorresponding to σ(x)=S1 x² +S1² x+S1³ +S3, and inverting bits in saidreceiving sequence in accordance with said output signal, therebycorrecting errors in said receiving sequence.